This invention relates to a communication system between a plurality of computer systems (subsystems), particularly to an inter-subsystem communication system which realizes highly efficient data transfer by making it no longer necessary to issue the start input/output device instruction (SIO instruction) for each data transfer and by minimizing the number of times interruptions are generated.
For an inter-subsystem connection system, an inter-subsystem connecting system connects by means of a inter-channel connecting system channel to channel adapter CTCA as illustrated in FIG. 1 and the connecting system utilizing communication between multiprocessors as illustrated in FIG. 2 are conventionally used.
In each system a main storage, a CPU and a channel form respective subsystems and the CTCA establishes the communication link connecting the subsystems. When the start IO instruction SIO is issued starting the inter-subsystem communication by the CPU of one subsystem to a channel of the same subsystem, a channel reads the channel address word CAW stored in main storage, decodes the contents of a channel control word CCW in the address specified by the channel address word CAW, and executes the channel input/output sequence.
The inter-subsystem connecting system by using the CTCA has the following disadvantages
(i) CTCA operations can be initiated only by the CCW and such operations do not have a high grade intelligence since they are limited because: (1) A chain of CCWs must be generated each time a message needs to be transferred; and (2) Queuing is managed by an I/O control program in the CPU not the CTCA. PA1 (ii) Termination of the CTCA operation is always communicated to the CPU by means of an interruption method and therefore transfer overhead caused by interruption processing becomes large in the CPU. PA1 (iii) It is difficult for the CPU to designate a priority sequence for the channel execution programs since they are executed sequentially. PA1 (I) In the case of the SIG-P instruction, when an interruption is issued specifying the particular processor and the message issuing subsystem must check the condition of the subsystem to be interrupted and judge whether the message receiving processor and can be interrupted. PA1 (II) Since the subsystems are tightly coupled, it is difficult to increase the physical distance between subsystems and thus the efficiency is degraded. PA1 (1) A software protocol at a logically high level is used for communication between subsystems. PA1 (2) The number of interruptions required for inter-subsystem communication are minimized. PA1 (3) Requests are transmitted to subsystems in accordance with a priority and priority processing is carried out correctly between subsystems. PA1 (4) Degradation of efficiency and increases in the amount and complexity of hardware in a long inter-subsystem physical distance are minimized. PA1 (5) Recovery processing when a hardware error has occurred is done efficiently by the operating system software. PA1 (6) Highly efficient data transfer and high speed response characteristics can be assured. PA1 (7) Wide application to total systems varying from a simple inter-system coupling to a complex system is possible, in addition, the total system structure utilizes the special purpose subsystems.
FIG. 2 is a block diagram illustrating a conventional example of the I/O subsystem as structured in the conventional multiprocessor system.
In FIG. 2, the left half is the host subsystem, while the right half is the I/O subsystem.
Main storage stores instructions for CPU.sub.1 and CPU.sub.2, data for CPU.sub.1 and CPU.sub.2, instructions for I/O processor IOP.sub.1 and IOP.sub.2, data for I/O processor IOP.sub.1 and IOP.sub.2, and the data for communication to I/O devices and between multiprocessing systems. Into the area storing data (information) for communication, for example, the contents of the data to be sent to the subsystem by the host system are written. When the SIG-P (signal processor) instruction is issued to the subsystem from the host system an interruption is scheduled for the I/O processor IOP.sub.1 or IOP.sub.2, at the interrupt the I/O processor IOP.sub.1 or IOP.sub.2 reads the data (information) written in the storage area and operates to execute the SIG-P instruction for the contents of the storage area. In the system indicated in FIG. 2, the information in the SIG-P (a signal processor) instruction stored in the common memory forms the communication means. FIG. 2 has the following problems: